This invention relates to a multi-chip or stacked integrated circuit (IC) die device. More specifically, this invention is directed toward a multi-chip device having a plurality of IC die, for example, a plurality of memory die, a controller die and memory die, or a processor, controller and plurality of memory die.
One conventional technique employed to provide greater IC densification includes incorporating several IC die into a single package. There is demand for larger IC densification to more fully utilize system layout space for applications such as portable computers and cell phones. An attractive solution is offered by vertical integration of IC die. That is, a three-dimensional approach where IC die are disposed one on top of another to more fully utilize a vertical dimension.
With reference to FIG. 1, a conventional multi-chip device 100 having a plurality of IC die 110 and 120 disposed one on top of another is illustrated. IC die 110 is stacked on top of IC die 120 which is disposed on base or substrate 130. A plurality of bond wires 140a-140d electrically couple pads disposed on IC die 110 to pads disposed on IC die 120. Similarly, a plurality of bond wires 150a-15m electrically couple pads disposed on IC die 120 to pads disposed on base 130.
The physical configuration of multi-chip device 100 tends to relax demands on system layout space. By disposing the IC die (e.g., memory die) vertically, only a single IC die footprint is required thereby resulting in a reduction in system layout space from a lateral or horizontal perspective Signal lines 140a-140d for example, control lines and address/clock lines are routed vertically between the IC die 110 and 120.
Contemporary stacked die configurations tend to minimize the length of the signal line path. That is, the contemporary approach for stacked die configurations, is to minimize the electrical path length of the signal lines. A stacked die configuration which seeks to minimize the length of the signal lines is described and illustrated in U.S. Pat. Nos. 5,675,180 and 5,698,895.
Contemporary stacked die configurations, like those described and illustrated in U.S. Pat. Nos. 5,675,180 and 5,698,895, employ a minimum signal line path length in order to decrease propagation delay of the signals on those lines. Decreasing the propagation delay tends to decrease the travel time of the signal between the die and, in turn, increase the speed of operation of the overall system.
In addition to presenting a minimum propagation delay of the signals applied to the signal lines, stacked die configurations employing a minimum signal line path length tend to minimize parasitic capacitance and inductance resulting from the interconnects. In general, this approach may promote faster operation because signal line lengths and corresponding propagation delays are reduced.
FIG. 2A is a schematic diagram of a plurality of conventional IC die in a stacked die configuration coupled to a signal line employing minimal conductor length between each IC die. Here the plurality of IC die 310a-310d are inter-coupled via conductors 320a-320d, respectively. Conductors 320a-320d represent a signal line. Load capacitances 330a-330d represent the load capacitance presented by IC die 310a-310d which are coupled to the signal line. In this regard, when electrically coupling IC die to signal bussing, the signal lines become loaded with the inherent load capacitance which is due to the various elements of the I/O structures disposed on the integrated circuit, for example, bond pads, electrostatic discharge protection devices, input buffer transistor capacitance, and output driver transistor parasitic and interconnect capacitances relative to the memory device substrate.
Because the length of conductors 320a-320d are minimized, conductors 320a-320d exhibit, as a practical matter, negligible inductance. Thus, load capacitances 330a-330d are effectively lumped producing a large overall equivalent or lumped capacitive characteristic. Here, the capacitive characteristic is present between a ground plane 340 which is common to IC die 310a-310d and conductors 320a-320d. 
One method for providing an increase in bandwidth and overall performance of a memory system, is to increase the effective data rate at which data may be transferred to and from each memory device (i.e., the data rate). In memory systems, one conventional approach to achieve such an increase is to increase the clock rate of the system, which tends to increase the data rate of the system and, in turn, the bandwidth.
However, as the data rate increases in multi-chip devices which seek to minimize signal line lengths, the lumped capacitive characteristic mentioned above requires increasingly more drive capability from output drivers of the IC die 310a-310d attempting to drive data onto conductors 320a-320c at an increased rate. That is, as the data rate increases, a relatively large amount of current is necessary in the same given period of time to drive the large overall lumped capacitive characteristic at a faster rate. Driver current for an output driver transmitting on an un-terminated lumped capacitive load is illustrated in FIG. 2B. The current demand from drivers of the signal line correspondingly increases with an increase in data rate for a given lumped load capacitance.
As data rates increase in systems employing minimal or short signal lines between IC die of a stacked die device, the number of IC die which may be coupled along the signal line decrease. As mentioned above, minimal or short signal lines between IC die of a stacked die device tend to result in negligible inductance separating each load capacitance along the signal line. Since each IC die increases the overall lumped load capacitance of the signal line in such a system, the maximum practical number of IC devices which may be coupled to the same signal line tends to become constrained or limited by the drive capability of the drivers on the IC die.
Stacked die configurations employing a minimal conductor length provide relatively fast access times. These configurations, however, suffer a number of shortcomings including a limitation on the maximum practical number of IC devices which may be coupled to the same signal linexe2x80x94i.e., a limit on the amount of vertical integration. That is, the minimum interconnect stacked die configurations place high demands on the necessary output drive which imposes an operation speed limitation on the system or a limitation on the number of devices or die coupled to the signal line. Thus, there is a need to provide an effective configuration which has fast access times, increases the operation speed of a multi-chip or stacked die device, and provides more flexibility in vertical integration.
The present invention relates to a high speed multi-chip device featuring a plurality of integrated circuit die on a base and/or housed in a semiconductor package. In one example, the present invention may be implemented in a memory system incorporating a plurality of memory devices into one or more multi-chip device(s). The present invention employs circuitry and techniques to increase the IC densification and space utilization of, for example, systems implemented on a circuit board. To this end, the present invention employs the vertical dimension to more fully optimize space usage.
The present invention may also be employed to increase computer system operation speed or to provide a high speed memory system. By employing interconnect conductors which include greatly reduced stub lengths and are optimized for high speed operation, the present invention may provide increased data rates and density. Using the approach of the present invention, demands on output drive-ability are more relaxed, thus more devices may be coupled into a system incorporating the techniques of the present invention.
In one aspect, the present invention includes a multi-chip device having a first integrated circuit die, a second integrated circuit die, and a first transmission line. The second integrated circuit die is stacked on the first integrated circuit die. The first transmission line is defined between a first end and a second end, wherein the first end is electrically connected to a first terminal and the second end is electrically connected to a second terminal. A first characteristic impedance is defined between the first terminal and the second terminal. A first conductive pad disposed on the first integrated circuit die, the first conductive pad being electrically connected to a first point on the first transmission line. A second conductive pad disposed on the second integrated circuit die, the second conductive pad being electrically connected to a second point on the first transmission line. A second transmission line may be electrically connected; to the first terminal, the second transmission line having a second characteristic impedance, the second characteristic impedance being matched to (within 70 and 130 percent of) the first characteristic impedance. In addition, a third transmission line may be electrically connected to the second terminal, the third transmission line having a third characteristic impedance, the third characteristic impedance being matched to (within 70 and 130 percent of) the first characteristic impedance.
In another aspect, the present invention includes a multi-chip device having a first and second integrated circuit die stacked and disposed on a base. A first conductor electrically connects the bond pad of the first integrated circuit die to the bond pad of the second integrated circuit die. A first external lead is electrically coupled to the first bond pad and a second external lead is electrically coupled to the second bond pad. The first conductor may be included as a portion of a transmission line. According to this aspect of the present invention, the transmission line may include a characteristic impedance in the range of between 10 to 75 ohms.
In yet another aspect of the present invention, a multi-chip device includes a plurality of integrated circuit die disposed in a stack configuration. Here, each integrated circuit die includes a plurality of bond pads. Each bond pad may be disposed at a periphery region of each integrated circuit die. According to this aspect of the present invention, a transmission line is disposed of a plurality of conductors, each conductor electrically connecting two bond pads. Here, each bond pad of the two are disposed on a pair of adjacent integrated circuit die. A termination element (e.g., a resistor) is connected to an end of the transmission line to terminate the transmission line to a termination voltage. The resistance of the termination element may be matched to the characteristic impedance of the transmission line.
The present invention is described in the detailed description, including the embodiments to follow. The detailed description and embodiments are given by way of illustration only. The scope of the invention is defined by the attached claims. Various modifications to the embodiments of the present invention remain within the scope defined by the attached claims. For example, the plurality of integrated circuit die may be one of a number of different types of integrated circuit devices. Also, the plurality of integrated circuit die may be stacked vertically or horizontally and the edges of adjacent integrated circuit die may be disposed with or without relative dimensional offset with respect to each other.